The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device (memory device) whose respective pair of bit lines is divided into a plurality of blocks each comprising memory cells, a sense amplifier, and switching elements.
Recently, memory devices have a great deal of memory capacity, so that the amount of memory cells in a device tremendously increases with a lot of word lines and bit lines connected to the memory cells. Accordingly, the stray capacitance distributed along the word and bit lines increases, which lowers the operation speed of the memory device. This problem with the bit line (usually a pair of bit lines) has been improved by dividing the pair of bit lines into a plurality of blocks. One improvement has been disclosed in Japanese Laid-open Patent Application No. 59-101093 in 1984. One difference between the present invention and the Laid-open Patent Application is that the driving ability of the sense amplifier in respective blocks is changed in the present invention. On the otherhand, in the Laid-open Patent, all the sense amplifiers have an equal driving ability.
FIG. 1 is a block and circuit diagram of a part of a usual memory device. Memory cells in the usual memory device, having the memory capacity of 64 kilo (K) bits or 256 K bits are arranged in a matrix as shown in FIG. 1, in which reference symbols C.sub.00, C.sub.01, - - - , and C.sub.0n are memory cells in a 0-th column; C.sub.10, C.sub.11, - - - , C.sub.1n are memory cells in a 1-st column; C.sub.i0, C.sub.i1, - - - , and C.sub.in are memory cells in an i-th column; and C.sub.n0, C.sub.n1, - - - , and C.sub.nn are memory cells in an n-th column. Each memory cell is positioned at each cross point of a respective word line and a pair of bit lines where reference symbols WD.sub.0, WD.sub.1, - - - , and WD.sub.n are the 0-th, the 1-st, - - - , and the n-th word line respectively, and BL.sub.0, BL.sub.0 ; BL.sub.1, BL.sub.1 ; - - - ; BL.sub.i, BL.sub.i ; - - - ; BL.sub.n , BL.sub.n are the 0-th, the 1-st, - - - , the i-th, - - - , and the n-th pair of bit lines respectively. Each pair of bit lines has a respective column decoder where a reference symbol CD.sub.i, shown in FIG. 1, is a column decoder for the i-th pair of bit lines. Similarly, each word line has a respective word decoder where a reference symbol WD.sub.i, in FIG. 1, is a word decoder for the i-th word line. When the memory device is in a read mode and word line select signals X.sub.0, X.sub.1, - - - , and X.sub.n and column select signals Y.sub.0, Y.sub.1, - - - , and Y.sub.n are applied to the word and the column decoders, a designated memory cell is selected and a data signal stored in the designated memory cell is read out. For example, when word decoder WD.sub.i and column decoder CD.sub.i function together by the word line and column select signals X.sub.i and Y.sub.i respectively, the data signal stored in memory cell C.sub.ii is read out and column decoder CD.sub.i functions for sending the read out data signal to a pair of data bus DB, DB. The read out data signal sent to the data bus DB, DB is amplified by a sense amplifier SA placed in data bus DB and DB.
However, when the memory capacity of the memory device increases as much as mega (M) bits, the number of memory cells also increases, and the stray capacitance distributed along each pair of bit lines also increases when compared with the memory capacitance provided in each memory cell. Thus, the operation speed of the memory device for writing or reading a data signal into or out from the memory cell is lowered and it becomes difficult to obtained a good signal to noise ratio. This causes a reduction in the operational reliability of the memory device. To obliterate the problem, the technique of dividing each pair of bit lines into a plurality of blocks has been developed. FIG. 2 shows a case of dividing the i-th pair of bit lines BL.sub.i, BL.sub.i into k blocks like BK.sub.i0, BK.sub.i1, - - - , and BK.sub.ik. In FIG. 2, each block comprises a pair of divided bit lines, a plurality of parted memory cells, a block sense amplifier, and a pair of switching elements. For example, block BK.sub.ik has a pair of divided bit lines BL.sub.ik, BL .sub.ik, a plurality of parted memory cells C.sub.ik0, C.sub.ik1, - - - , and C.sub.ikm, a block sense amplifier SA.sub.ik, and a pair of switching elements S.sub.ik, S.sub.ik, where, the number "m" is set so that the number "n" shown in FIG. 1 is equal to "k" times as many as "m".
In FIG. 2, when one of the parted memory cells is selected by one of the word select signals X.sub.0 .about.X.sub.n (see FIG. 1), one of the block select signals BS.sub.i0, BS.sub.i1, - - - , and BS.sub.ik is designated, and the designated block select signal activates a block sense amplifier in the selected block. Then, the selected block sense amplifier amplifies a data signal stored in the selected memory cell. Pairs of switching elements S.sub.i0, Si0; S.sub.i1, S.sub.i1 ; - - - ; and S.sub.ik, S.sub.ik are inserted in the pairs of bit lines in the blocks respectively for connecting the blocks in series. Column decoder CD.sub.i is inserted between a block (BK.sub.ik), which is nearest to the pair of bus lines DB, DB, and the pair of bus lines DB, DB. When column select signal Y.sub.i designates the i-th column, transfer gates Q.sub.1 and Q.sub.2, provided in column decoder CD.sub.i, turn ON for sending the data signal, which is amplified by the selected block sense amplifier, to the pair of bus lines DB, DB.
Further detail of circuits in the block and its operation will be explained with reference to FIG. 3 when the memory device is in the read mode.
FIG. 3(a) is a bit line pre-charge circuit provided in respective block, while FIGS. 3(b) and 3(c) are the switching elements either one of which is provided in the respective block. FIGS. 3(a), 3(b), and 3(c) show a block BK.sub.i0. FIG. 3(a) shows a pre-charge circuit PRE.sub.i0 which comprises transistors Q.sub.i01, Q.sub.i02, and Q.sub.i03 for applying equally pre-charging potential (V.sub.cc -V.sub.th) onto pair of bit lines BL.sub.i0, BL.sub.i0 when a pre-charge signal p is applied to the gates of transistors Q.sub.i01, Q.sub.i02, and Q.sub.i03. A transistor Q.sub.i04 shown in FIG. 3(b) is for switching element S.sub.i0 or Si0 shown in FIG. 2. The transistor Q.sub.i04 turns ON when a clock signal .phi. is applied to its gate. FIG. 3(c) also shows another type of the switching element which consists of a transistor Q.sub.i04, which is the same as the one in FIG. 3(b), and a transistor Q.sub.i05, which is connected in parallel to the transistor Q.sub.i04. Transistor Q.sub.i05 is a reverse conduction type transistor when compared to transistor Q.sub.i04. The switching element turns ON when clock signals .phi., .phi. are simultaneously applied to the gates of transistors Q.sub.i04 and Q.sub.i05 respectively.
The circuit of FIG. 2 sequentially operates in following steps: (1) one word line is selected by a word line select signal X.sub.0, X.sub.1, - - - , or X.sub.n (see FIG. 1); for example, a word line WL.sub.0 is selected by word line select signal X.sub.0 ; (2) one column is selected by a column select signal Y.sub.0, Y.sub.1, - - - , or Y.sub.n ; for example, column i is selected by column select signal Y.sub.i ; (3) a memory cell located at a cross point of the selected word line and column is selected; for example, memory cell C.sub.i00 in block BK.sub.i0 is selected; (4) one block select signal is provided when a word line and a column are selected; for example, block select signal BS.sub.i0 is selected; (5) one block sense amplifier is activated by the block select signal, so that a voltage difference appearing between bit lines in the selected block is amplified; for example, block sense amplifier SA.sub.i0 is activated by block select signal BS.sub.i0, so that a voltage difference appearing between bit lines BL.sub.i0, BL.sub.i0 is amplified; (6) after the voltage difference is amplified by the selected block sense amplifier, all switching elements in the selected column are turned ON so that all blocks of the selected column are connected in series; for example, after the voltage difference appearing between bit lines BL.sub.i0, BL.sub.i0 is amplified by block sense amplifier SA.sub.i0, all switching elements S.sub.i0, S.sub.i0 ; S.sub.i1, S.sub.i1 ; - - - ; and S.sub.ik, S.sub.ik are turned ON so that all blocks BK.sub.i0, BK.sub.i1, - - - , and BK.sub.ik are connected in series; and (7 ) the transfer gates in a column decoder belonging to the selected column are turned ON by a column select signal for feeding the amplified data signal onto data bus DB, DB; for example, transfer gates Q.sub.i1, Q.sub.i1 in column decoder CD.sub.i are turned ON by column select signal Y.sub.i for feeding the amplified data signal onto data bus DB, DB.
In the above explanation (6), "all switching elements" are not always turned ON, but at least the switching elements in the selected block and in the blocks locating between the selected block and column decoder CD.sub.i are turned ON.
In addition, in the prior art, all other block sense amplifiers can be activated after the selected block sense amplifier has been activated and the switching elements have been turned ON.
As explained above, in the prior art, the load capacitance for the sense amplifier can be kept small the first time the block sense amplifier in the selected block is activated. However, when the blocks locating between the selected block and column decoder CD.sub.i are connected to the data bus, the load capacitance for the selected block sense amplifier increases. For example in FIG. 2, when block BK.sub.i0 is selected and sense amplifier SA.sub.i0 is activated and the switching elements connect the all blocks, the load capacitance becomes a total sum of capacitance along the bit lines in column i. Accordingly, the sense amplifier in the farthest block from the data bus, for example sense amplifier SA.sub.i0 in block BK.sub.i0, must have a great enough driving ability to amplify the voltage difference in a short enough time. Furthermore, each sense amplifier has an equal driving ability, so if a sense amplifier in the nearest block from the data bus, for example sense amplifier SA.sub.ik in block BK.sub.ik, is selected, the sense amplifier (SA.sub.ik) wastes too much power, which has been a problem in the prior art.